Spectre rears its ugly head again as researchers show some RISC-V chips are susceptible
- ID
- 13692
- Status
- summarized
- Published
- 13 Aug 2026, 3:42 AM
- Fetched
- 13 Aug 2026, 6:05 AM
- Provider
- The Register
- Category
- technology
- Original URL
- https://www.theregister.com/security/2026/08/12/spectre-rears-its-ugly-head-again-as-researchers-show-some-risc-v-chips-are-susceptible/5286978
- Source URL
- https://www.theregister.com/headlines.atom
Summary
- Score
- 4.5
- Created
- 13 Aug 2026, 7:09 AM
- Tags
- Audience
- developersai_ml_learners
What happened
Researchers from Belgian and German academic institutions demonstrated at the 35th Usenix Security Symposium that commercial out-of-order RISC-V processors—specifically SiFive P550 and T-Head Xuantie C910/C920—are vulnerable to all major Spectre variants (PHT, BTB, RSB, STL), achieving up to 100% recall and 97%+ precision in proof-of-concept attacks. In-order RISC-V processors (SiFive U74, Xuantie C906, C908) appear unaffected.
Why it matters
If you're evaluating RISC-V silicon for embedded or edge deployments, prefer in-order cores (U74, C906, C908) over out-of-order ones (P550, C910/C920) if Spectre-class side-channel leakage is a threat model concern. The T-Head Xuantie C910/C920 chips are Alibaba's designs and are among the more accessible commercial RISC-V parts in Asia, so builders sourcing from regional distributors should factor in that mitigations are not yet mature compared to the x86/ARM ecosystem.
Discussion angle
RISC-V is often pitched as a clean-slate architecture free of legacy security baggage—this paper punctures that assumption for out-of-order designs. Worth discussing whether the simplicity argument holds for any architecture once you add speculative execution for performance.