A third world engineer responds to “RISC-V: They should have known better”
- ID
- 14678
- Status
- summarized
- Published
- 17 Aug 2026, 1:01 AM
- Fetched
- 19 Aug 2026, 1:57 AM
- Provider
- Hacker News
- Category
- dev-community
- Original URL
- https://rvembedded.com/blog_post/12/
- Source URL
- https://hnrss.org/best
Summary
- Score
- 4.5
- Created
- 19 Aug 2026, 3:03 AM
- Tags
- Audience
- developers
What happened
An embedded engineer responds to Dmitry Grinberg's widely-discussed criticism of RISC-V, pushing back on what they see as a biased perspective despite acknowledging some valid technical complaints like compressed store offsets. The author switched their entire stack from STM32/ARM to RISC-V CH32 chips about a year ago and argues from that hands-on experience.
Why it matters
If you're building IoT or embedded devices on a budget, the CH32V003 and similar RISC-V MCUs are a real cost-alternative to STM32/ARM, but this debate highlights genuine ISA-level tradeoffs you should understand before committing. The compressed store offset issue is a concrete gotcha worth knowing if you're evaluating RISC-V for production firmware.
Discussion angle
Is RISC-V worth the migration cost for Malaysian IoT/embedded builders when STM32 clones are already cheap and well-tooled, or is this still a hobbyist play?