Hot Chips 2026: SK hynix pushes hybrid bonding HBM5 as AI memory hits 775-micron ceiling — firm extends MR-MUF through Nvidia Rubin
- ID
- 17329
- Status
- summarized
- Published
- 25 Aug 2026, 1:55 AM
- Fetched
- 25 Aug 2026, 4:06 AM
- Provider
- Tom's Hardware
- Category
- technology
- Original URL
- https://www.tomshardware.com/tech-industry/semiconductors/sk-hynix-says-hybrid-bonding-wont-be-ready-for-hbm4e-as-ai-memory-runs-into-a-775-micron-ceiling
- Source URL
- https://www.tomshardware.com/feeds/all
Summary
- Score
- 4.5
- Created
- 25 Aug 2026, 4:10 AM
- Tags
- Audience
- ai-ml-learnerssaas-startup-founders
What happened
At Hot Chips 2026, SK hynix VP Jaesik Lee said hybrid bonding won't be ready for HBM4E, pushing the packaging transition to HBM5 at the earliest. HBM stack height is physically capped at 775 microns (the thickness of a 300mm logic wafer), so 16-Hi HBM4—now in customer qualification at 48GB per cube—thins core dies to ~50 microns and halves inter-die gaps versus the 12-Hi part already in mass production. SK hynix is extending its MR-MUF process through Nvidia Rubin, and its iHBM cooling architecture cannot be retrofitted onto any HBM generation already in design.
Why it matters
If you are planning AI training or inference capacity over a 2-3 year horizon, expect HBM4E to rely on existing MR-MUF scaling rather than hybrid bonding, meaning incremental density gains but no packaging leap until HBM5. The 775-micron ceiling means memory capacity per cube grows slowly through die-thinning, not stack-count explosion—so GPU memory budgets for large models will remain tight and expensive for longer than roadmap slides imply.
Discussion angle
What does the 775-micron ceiling mean for AI builders who assume memory capacity will keep climbing—should you design model architectures and serving strategies around 48GB-per-cube constraints for the next two generations?