Hot Chips 2026: Fujitsu's Monaka CPU stacks its entire cache on a separate 5nm die and narrows to 256-bit SVE2 — 350W and 500W SKUs due in 2027
- ID
- 18138
- Status
- summarized
- Published
- 26 Aug 2026, 9:30 PM
- Fetched
- 26 Aug 2026, 9:35 PM
- Provider
- Tom's Hardware
- Category
- technology
- Original URL
- https://www.tomshardware.com/pc-components/cpus/fujitsus-monaka-cpu-stacks-its-entire-cache-on-a-separate-5nm-die-and-narrows-to-256-bit-sve2
- Source URL
- https://www.tomshardware.com/feeds/all
Summary
- Score
- 3.5
- Created
- 26 Aug 2026, 9:36 PM
- Tags
- Audience
- developersai_ml_learners
What happened
Fujitsu detailed its 144-core Arm Monaka server CPU at Hot Chips 2026, confirming dual 256-bit SVE2 vector units (down from 512-bit SVE in the A64FX) and a novel packaging approach where the entire last-level cache sits on a separate 5nm die beneath the 2nm compute die. Two SKUs ship in 2027: a 350W air-cooled part at 2.1 GHz base and a 500W liquid-cooled part at 2.9 GHz base, with evaluation samples available now. The project is subsidized by Japan's NEDO and positioned for 'green AI data centers.'
Why it matters
For most builders this is informational, not actionable — Monaka targets specialized HPC/AI infrastructure and won't appear in standard cloud instances Malaysian developers use. The one signal worth noting is Fujitsu halving vector width from 512-bit to 256-bit SVE2, which suggests the industry is converging on 256-bit as the practical default for Arm server vector code; if you're writing portable SVE2 code, target 256-bit.
Discussion angle
Why did Fujitsu halve vector width from 512-bit SVE to 256-bit SVE2 — is this a concession that 512-bit was too niche, and does it signal that 256-bit SVE2 is becoming the de facto target for portable Arm server SIMD code?