Samsung's Processing-in-Memory (PIM)
- ID
- 19448
- Status
- summarized
- Published
- 29 Aug 2026, 2:06 PM
- Fetched
- 31 Aug 2026, 6:41 AM
- Provider
- Hacker News
- Category
- dev-community
- Original URL
- https://chipsandcheese.com/p/hot-chips-2026-samsungs-processing
- Source URL
- https://hnrss.org/best
Summary
- Score
- 5.0
- Created
- 31 Aug 2026, 6:45 AM
- Tags
- Audience
- ai-ml-learnersdevelopers
What happened
Samsung presented their LPDDR5X-PIM architecture at Hot Chips 2026, placing MAC units inside each of 16 DRAM banks on standard LPDDR5X-9600 chips to exploit internal bandwidth of 614 GB/s versus 76.8 GB/s for normal external access. Each PIM block contains a MAC tree with 1024-bit instruction registers and supports INT8, FP8, and 4-bit formats, yielding 2.4 TOPS per chip at 4-bit; eight chips together reach 9.6 INT8 TOPS, roughly matching Intel Meteor Lake's NPU, but requiring 128 GB of LPDDR5X. Crucially, PIM operations are invoked using standard LPDDR5X protocol commands, meaning no exotic memory controller is needed.
Why it matters
For builders working on edge AI or mobile inference, PIM could eventually reduce the memory-bandwidth bottleneck that limits large-model deployment on constrained devices—but at 2.4 TOPS per chip and with no shipping product timeline given, there is nothing to adopt or design around today. The most actionable detail is that Samsung is keeping the interface standard LPDDR5X, which means future PIM-aware software stacks could target existing memory controllers rather than requiring custom hardware.
Discussion angle
Whether in-memory compute like PIM will matter for the edge AI devices Malaysian startups might build, or whether existing NPUs and mobile SoCs already close the gap for practical model sizes—given that 9.6 INT8 TOPS from eight LPDDR5X chips is only on par with a current-generation laptop NPU.