ASML and TSMC want bigger masks for smaller chips
- ID
- 22407
- Status
- summarized
- Published
- 08 Sep 2026, 11:02 PM
- Fetched
- 08 Sep 2026, 11:20 PM
- Provider
- The Register
- Category
- technology
- Original URL
- https://www.theregister.com/systems/2026/09/08/asml-and-tsmc-want-bigger-masks-for-smaller-chips/5294982
- Source URL
- https://www.theregister.com/headlines.atom
Summary
- Score
- 3.5
- Created
- 08 Sep 2026, 11:20 PM
- Tags
- Audience
- developerssaas_founders
What happened
ASML and TSMC are collaborating to move EUV lithography from 6-inch to 12-inch photomasks, with a pilot line targeted by 2031 and production-ready systems by 2033. The larger masks would restore the full exposure field that ASML's anamorphic high-NA optics halved, eliminating costly stitch-together patterning for large dies and improving fab productivity. Intel Foundry and Samsung have also backed the initiative.
Why it matters
This sets the hardware supply-chain trajectory for advanced-node chips through the early 2030s — if your roadmap depends on next-generation silicon availability or pricing, expect high-NA EUV to start on 6-inch masks with a later transition to 12-inch, meaning large-die designs may face stitching constraints and higher costs until roughly 2033. No immediate action required for most builders.
Discussion angle
What the 6-to-12-inch mask transition means for cloud compute cost curves — if large-die chips stay expensive to produce until ~2033, does that slow the hardware price-perf improvements that SaaS margins have been riding on?