d-Matrix drinks the Nvidia Kool-Aid with NVLink Fusion and MGX rack designs
- ID
- 23150
- Status
- summarized
- Published
- 10 Sep 2026, 9:00 PM
- Fetched
- 10 Sep 2026, 9:12 PM
- Provider
- The Register
- Category
- technology
- Original URL
- https://www.theregister.com/systems/2026/09/10/d-matrix-drinks-the-nvidia-kool-aid-with-nvlink-fusion-and-mgx-rack-designs/5295403
- Source URL
- https://www.theregister.com/headlines.atom
Summary
- Score
- 5.5
- Created
- 10 Sep 2026, 9:13 PM
- Tags
- Audience
- developersai_ml_learnerssaas_startup_founders
What happened
AI inference chip startup d-Matrix has licensed Nvidia's NVLink Fusion interconnect and MGX rack reference designs, joining Qualcomm, Arm, Marvell, Amazon, Fujitsu, and MediaTek in the NVLink ecosystem. By end of next year, d-Matrix plans to ship NVL144 racks with 144 Raptor XPUs delivering ~2.3 TB of 3D-stacked DRAM capacity and ~7.2 PB/s aggregate memory bandwidth—enough for 4+ trillion parameter models at 4-bit precision. Each XPU bonds compute logic directly atop DRAM for in-memory compute, targeting the memory bandwidth bottleneck that dominates AI inference cost.
Why it matters
The NVLink Fusion licensing ecosystem is consolidating around Nvidia's rack-level fabric as the de facto standard for multi-chip inference, which means builders evaluating non-Nvidia inference accelerators (like d-Matrix's Raptor) can deploy them in existing MGX/NVSwitch racks rather than bespoke infrastructure. If you're planning inference capacity for large models, the in-memory compute approach here—100 TB/s per card vs ~22 TB/s on Rubin—suggests the next generation of inference hardware will be memory-bandwidth-first, and your workload benchmarking should weight memory bandwidth over raw FLOPS.
Discussion angle
Is the growing NVLink Fusion licensee list effectively making Nvidia the rack-scale interconnect monopoly even for competitors' chips, and does that reduce or increase vendor lock-in for inference infrastructure buyers?