Analyzing Intel's EMIB and Foveros advanced packaging roadmaps
- ID
- 35340
- Status
- summarized
- Published
- 14 Oct 2026, 8:50 PM
- Fetched
- 14 Oct 2026, 9:59 PM
- Provider
- Tom's Hardware
- Category
- technology
- Original URL
- https://www.tomshardware.com/tech-industry/semiconductors/analyzing-intels-emib-and-foveros-advanced-packaging-roadmaps-how-intel-plans-to-scale-chips-in-every-direction
- Source URL
- https://www.tomshardware.com/feeds/all
Summary
- Score
- 3.0
- Created
- 14 Oct 2026, 10:01 PM
- Tags
- Audience
- developers
What happened
Tom's Hardware published a member-exclusive feature by Anton Shilov analyzing Intel's EMIB (Embedded Multi-die Interconnect Bridge) and Foveros advanced packaging roadmaps. The available text only establishes background: Intel's packaging work began in 2017 with Kaby Lake-G CPUs and Stratix 10 FPGAs, and virtually all of Intel's high-end client and data center CPUs now depend on EMIB and Foveros. The actual forward-looking roadmap detail sits behind the paywall and is not present in the excerpt.
Why it matters
There is nothing actionable here for builders: no process nodes, no capacity numbers, no dates, no pricing, and no Malaysia or Southeast Asia angle appear in the text you can actually read. If you are tracking chip supply for AI accelerators or planning hardware-dependent work, this item gives you a headline and a 2017 starting point, not a decision input. Skip it unless someone with premium access summarizes the roadmap specifics.
Discussion angle
Worth a 60-second mention at most: ask whether anyone in the group has premium access and can pull the actual EMIB/Foveros scaling claims, since the free excerpt contains only the 2017 Kaby Lake-G and Stratix 10 origin story and no forward roadmap.