Who is vfmaddrnd231pd?
- ID
- 35533
- Status
- summarized
- Published
- 13 Oct 2026, 5:12 AM
- Fetched
- 15 Oct 2026, 4:23 AM
- Provider
- Hacker News
- Category
- dev-community
- Original URL
- https://purplesyringa.moe/blog/who-is-vfmaddrnd231pd/
- Source URL
- https://hnrss.org/best
Summary
- Score
- 4.5
- Created
- 15 Oct 2026, 4:23 AM
- Tags
- Audience
- developers
What happened
A blog post investigates vfmaddrnd231pd, an FMA instruction documented in the 2024 Intel Software Development Manual that allows per-instruction rounding control without AVX-512 — but which does not actually exist. GNU assembler rejects it, the _mm_fmaddround_pd/_mm256_fmaddround_pd intrinsics are missing from Clang and even Intel's own ICC, its VEX opcode notation references a 'DDS' token that appears nowhere else in the SDM, and executing it on a Haswell CPU raises #UD. The author notes the instruction is simply absent from the 2026 edition of the SDM, and an update credits commenters with tracing the story back to AVX10, which Intel introduced after failing to bring AVX-512 to consumer CPUs in 2023.
Why it matters
If you write SIMD codegen, JIT backends, or disassembler/assembler tooling, this is a concrete reminder that a published Intel SDM opcode table is not a guarantee of silicon: vfmaddrnd231pd was in the 2024 SDM, gone from the 2026 edition, unsupported by any assembler or compiler intrinsic, and faults with #UD on FMA-capable hardware. Cross-check the current SDM edition and test on real CPUs before encoding anything you found in an older manual revision. There is no Malaysian or Southeast Asian angle in this item.
Discussion angle
Vendor documentation drifting from shipping silicon: what is your process for validating an ISA or API claim from a spec before you build on it — and does the AVX10 origin story change how you'd bet on future instruction sets?