Micron plans to use wafer bonding and High-NA EUV for next-gen DRAM
- ID
- 39557
- Status
- summarized
- Published
- 26 Oct 2026, 10:00 PM
- Fetched
- 26 Oct 2026, 10:39 PM
- Provider
- Tom's Hardware
- Category
- technology
- Original URL
- https://www.tomshardware.com/pc-components/dram/micron-plans-to-use-wafer-bonding-and-high-na-euv-for-next-gen-dram-company-also-developing-vertical-high-bandwidth-memory-and-vertical-edge-inference-memory-integrated-directly-on-top-of-processors
- Source URL
- https://www.tomshardware.com/feeds/all
Summary
- Score
- 3.5
- Created
- 26 Oct 2026, 10:41 PM
- Tags
- Audience
- developersai_ml_learnerssaas_founders
What happened
Tom's Hardware reports that Micron plans to use wafer bonding and High-NA EUV lithography for next-generation DRAM. The piece also says Micron is developing vertical high-bandwidth memory and a vertical edge-inference memory designed to sit directly on top of processors. Beyond those claims there are no figures, timelines, capacity numbers, or product names in the available text — the page body is mostly subscription navigation.
Why it matters
There is not enough here to act on: no dates, densities, pricing, or part numbers, so you cannot yet plan around cost-per-GB, HBM supply, or on-device inference memory budgets. Treat it as a directional signal that memory stacking is heading toward processor-adjacent packages, and wait for Micron's own technical disclosures before changing hardware assumptions or quoting memory costs to clients.
Discussion angle
If edge inference memory really lands stacked on top of the CPU/GPU package, which of your current workloads (local models, on-device agents, latency-sensitive APIs) would move off cloud — and what would you need to know about capacity and price before committing?