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25 Aug 2026, 5:07 AMTom's Hardware4.0 Hot Chips 2026: Intel Xeon 7 'Diamond Rapids' comes with up to 256 P-cores, 1.28 GB of last-level cache — next-gen 18A-P CPU also brings AVX 10.2 and uses UCIe-S instead of EMIB

Intel announced Xeon 7 'Diamond Rapids' at Hot Chips 2026, scaling to 256 P-cores with 1.28 GB of last-level cache, built on the 18A-P process. The chip adds AVX 10.2 instruction support and switches from EMIB to UCIe-S for die-to-die interconnect.

Why: If you run CPU-based inference or heavy multi-threaded workloads on cloud instances, the 1.28 GB LLC and AVX 10.2 support could meaningfully change per-core throughput for large-model inference and vectorized workloads once this ships. The UCIe-S shift signals Intel moving toward an open chiplet standard, which matters for anyone evaluating long-term infrastructure lock-in, but this is a pre-announcement with no pricing, availability date, or benchmarks.

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