GlobalFoundries VP details FDX Fusion technology, sporting 7nm-class performance without the need for EUV tools — company targets 2030 for high-volume manufacturing, with planar transistors in tow
- ID
- 43815
- Status
- summarized
- Published
- 06 Nov 2026, 10:00 PM
- Fetched
- 06 Nov 2026, 10:42 PM
- Provider
- Tom's Hardware
- Category
- technology
- Original URL
- https://www.tomshardware.com/tech-industry/semiconductors/globalfoundries-vp-details-fdx-fusion-technology-sporting-7nm-class-performance-without-the-need-for-euv-tools-company-targets-2030-for-high-volume-manufacturing-with-planar-transistors-in-tow
- Source URL
- https://www.tomshardware.com/feeds/all
Summary
- Score
- 3.0
- Created
- 06 Nov 2026, 10:44 PM
- Tags
- Audience
- developers
What happened
GlobalFoundries VP Sudipto Bose, who leads the company's FD-SOI business unit, detailed FDX Fusion: a FD-SOI process claiming 7nm-class performance with advanced planar transistors and no EUV lithography, at 8nm-class logic density. Commercial production is targeted for 2028, with high-volume manufacturing aimed at 2030 — eight years after GlobalFoundries dropped its original 7nm FinFET effort. The trade-off stated in the piece is low transistor density relative to true 7nm nodes.
Why it matters
Nothing here changes a build decision today: the first commercial output is slated for 2028 and volume for 2030, and the process trades density (8nm-class) for avoiding EUV. The only actionable read for a Malaysian hardware-adjacent team is cost structure — non-EUV FD-SOI is aimed at cheaper die cost, so if you are scoping edge/IoT or RF silicon for a 2029-2030 product cycle, this is a candidate to price against, not a reason to delay anything shipping sooner.
Discussion angle
Roadmaps announced in 2026 for 2028 production and 2030 volume — how much weight should builders give a foundry promise when the same company exited 7nm once already, and does 'no EUV, 8nm-class density' ever beat plain cost-per-die on an older node?