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Date	Provider	Score	Summary
19 Aug 2026, 8:00 AM	The Register	5.0	Cerebras CS-4 rack systems juice chips for every last drop of AI performance Cerebras announced the WSE-3T, which doubles compute and memory bandwidth of its existing WSE-3 wafer-scale chip not with new silicon but by improving power delivery to push clock speeds from an estimated 1.4 GHz to 2.8 GHz, raising wafer TDP from 15 kW to ~33 kW. The headline 250 PFLOPS figure relies on 10x sparsity; dense FP16 is ~25 PFLOPS, and the article notes sparsity generally doesn't benefit LLM inference. Why: If you're evaluating AI inference hardware, don't compare Cerebras' sparse FPLOPS against Nvidia/AMD dense numbers—use the ~25 PFLOPS dense FP16 figure instead. The power-delivery trick (doubling clock on the same 5nm die) is notable, but the 33 kW per-wafer TDP means cooling and power costs are a real constraint for anyone considering these systems. ai-hardware inference cerebras performance-benchmarks

Date

Provider

Score

Summary

19 Aug 2026, 8:00 AM

The Register

5.0

Cerebras CS-4 rack systems juice chips for every last drop of AI performance

Cerebras announced the WSE-3T, which doubles compute and memory bandwidth of its existing WSE-3 wafer-scale chip not with new silicon but by improving power delivery to push clock speeds from an estimated 1.4 GHz to 2.8 GHz, raising wafer TDP from 15 kW to ~33 kW. The headline 250 PFLOPS figure relies on 10x sparsity; dense FP16 is ~25 PFLOPS, and the article notes sparsity generally doesn't benefit LLM inference.

Why: If you're evaluating AI inference hardware, don't compare Cerebras' sparse FPLOPS against Nvidia/AMD dense numbers—use the ~25 PFLOPS dense FP16 figure instead. The power-delivery trick (doubling clock on the same 5nm die) is notable, but the 33 kW per-wafer TDP means cooling and power costs are a real constraint for anyone considering these systems.